(1) Field of the Invention
This invention relates to a computer system with a peripheral component interconnect Express (PCI Express) interface, more particularly to a computer system adapting a high speed PCI Express interfaced apparatus to a relative low speed PCI Express connector.
(2) Description of Related Art
A computer system typically includes a main board with a system bus formed thereon as a basic component. Various devices including the central processing unit (CPU), the chipset, and memory on the main board are communicated with each other. The chipset plays an important role in ruling signal and data transmission through the system bus and some periphery buses. In the art, the choice of chipset is highly related to that of the CPU. In addition, there are also various connectors utilizing the periphery buses for connecting periphery components such as the displaying card, hard disks, floppy disks, CDROM, etc.
Referring to FIG. 1, there is a prior art computer system with a Northbridge (NB) 100 and a Southbridge (SB) 200. The NB 100 deals with data and signal transmission among the CPU 120, a main memory 140, and an accelerated graphic port (AGP) connector 160. The NB 100 also communicates with the SB 200 by using a particular transmission protocol. The SB 200 is provided with a PCI controller, an Integrated drive electronics (IDE) controller, an universal serial bus (USB) controller, and other specific controllers for ruling various periphery components such as a PCI connector 220, a CDROM/hard disk 240, a floppy disk 260 and a keyboard/mouse 280, so as to deal with the input/output (I/O) signals with the periphery components 220,240,260,280. Furthermore, the SB 200 also transmits some interrupt requests from the periphery components 220,240,260,280 to the NB 100 for asking the CPU 120 to set up a proper operation schedule dealing with the periphery components 220,240,260,280.
The AGP interface, which is developed to meet the need of handling huge data streams resulted from texture mapping in 3D imaging, is provided to overcome the transmission speed limitation of a traditional PCI interfaced displaying card. However, some advance PCI interfaced periphery components, such as small computer systems interface (SCSI) hard disks with ultra 320 standard and Ethernet adapters supporting transmission speed up to 10 GB, is not compatible with the AGP interface. Also, the operation of those PCI interfaced periphery components may surpass the allowable transmission speed of the traditional PCI interface. Therefore, as a result, a new I/O port interface, i.e. the PCI Express interface, is introduced.
The PCI Express interface, which is developed to replace traditional PCI interfaces, is provided with high transmission speed and great extensibility. For a better understanding, a typical computer system with a PCI Express interface is shown in FIG. 2. The chipset 110 in the computer system may connect to a PCI Express connector 330 with or without a switch 320, and further connect to some traditional PCI connectors 350 by using a bridge 340. Upon such an arrangement, the PCI Express interface can support traditional PCI interfaced apparatus and have potential to replace the PCI interface, or even the AGP interface.
The PCI Express interface featuring a serial point to point connection utilizes a low voltage differential signal (LVDS) (using two transmission lines to create a voltage differential to represent logic signal 0 or 1) transmission to increase the transmission speed with a reduced noise. Under the technique standard of the PCI Express interface, a basic PCI Express link specifies two LVDS, one for transmitting signals, and another for receiving signals. Such a link is also represented as a “lane” with a standardized bit rate of 2.5 Gbps.
As mentioned, it is known that the bandwidth as well as the transmission speed of the PCI Express interface is decided by the amount of lanes, and the increase in lanes implies an increase of contacts within the PCI Express connector. Moreover, it is disclosed that the PCI Express connector may have 1, 2, 4, 8, 12, 16, or 32 lanes and may have a selectable bandwidth ranged from 2.5 Gbps to 80 Gbps.
FIG. 3 shows a typical 1×PCI Express connector 330a, and FIG. 12 shows a relative contact definition table to the PCI Express connector 330a of FIG. 3. FIG. 4 shows a typical 4×PCI Express connector 330b, and on the other hand FIG. 13 shows a contact definition table related to FIG. 4. In the contact definition tables of FIGS. 12 and 13, label “RSVD” represents a preserved contact, label “GND” represents a grounding contact, labels “JTAG1” to “JTAG5” represent testing contacts, label “3.3Vaux” represents a contact for applying a 3.3V auxiliary power, labels “SMCLK” and “SMDAT” represent, respectively, a system management bus clock and a data that control data transmission between the connector and the controller, labels “REFCLK+” and “REFCLK−” represent contacts for delivering reference clock signals for generating differential pairs, labels “HSOp(i)” and “HSOn(i)” represent contacts for transmitting differential pairs, labels “HSIp(i)” and “HSIn(i)” represent contacts for receiving differential pairs, and labels “PRSNT#1” and “PRSNT#2” represent contacts for detecting if a hot plug is present.
As mentioned above and according to FIGS. 12 and 13, the 4×PCI Express connector 330b has four “lanes” to represent a bigger bandwidth than the 1×PCI Express connector 330a with only one “lane”. Comparing the contacts of FIG. 4 to that of the 1×PCI Express connector 330a (the contacts #1˜#18) in FIG. 3, the 4×PCI Express connector 330b has fourteen more contacts (the contacts #19˜#32) for providing more “lanes”. The additional contacts (the contacts #19˜#32) are aligned after a rear end of the original 1×PCI Express connector 330a; i.e. after the contact #18 as shown in FIG. 13.
Accordingly, by compared to the 1×PCI daughter board, the 4×PCI daughter board has a wider connecting portion for receiving the contacts of a connector. Therefore, though the PCI Express connector with a preset bandwidth can mate with a PCI Express daughter board with a relative bigger bandwidth, yet such a PCI Express daughter board is still far to be acceptable.
Moreover, the bandwidth of a PCI Express connector provided on the prior art main board is always identical to the maximum supporting bandwidth of the PCI Express controller inside the chipset. Thus, only the PCI Express daughter board with a smaller bandwidth with respect to the PCI Express controller on the main board is applicable. For example, in the case that the chipset on the main board supports only 1×PCI Express interface, a 1×PCI Express interface connector is definitely the only choice. At this time, a 2×PCI Express daughter board who has a bigger bandwidth cannot be accepted in this connector. It is why the misunderstanding that a PCI Express controller cannot operate with a PCI Express daughter board with a bigger bandwidth happens to retard the development of some periphery apparatuses utilizing the PCI Express daughter board.
Therefore, it is definitely of great demand upon how to break the limitation by the chipset standard so as to allow a PCI Express daughter board with a bigger bandwidth to be compatible with a PCI Express controller and a respective connector with a smaller lane.